Keynote talks

Detection & Diagnostics in Today’s Advanced Technology Nodes

Dr. Yervant Zorian's photo Yervant Zorian
Fellow & Chief Architect,
Synopsys

Abstract With the wide adoption of nanometer technologies, it has become crucial for today’s SOCs to use advanced test and diagnosis solutions. These solutions provide comprehensive detection of not only random defects, but also systematic and process variation defects often manifested under unique test corners. Moreover, with the adoption of FinFET technologies, these advanced solutions are extended to cover new FinFET specific defects. This keynote, besides discussing the key trends and challenges of advanced nanometer technologies, will cover solutions to handle the wide range of potential defects in today’s SOCs. It will also address post-silicon analysis and yield optimization trade-offs using volume diagnostic, failure coordinate calculation, reconfiguration and repair. With the proliferation of high-density packaging, such as 2.5D and 3D-ICs, this keynote will also cover testing and diagnosis of dies and interconnects, via advanced test solutions based on IEEE test access standards.

Author's bio Dr. Zorian is a Fellow and Chief Architect at Synopsys, Mountain View, California. Formerly, he was Distinguished Member of Technical Staff AT&T Bell Laboratories, Vice President and Chief Scientist of Virage Logic and Chief Technologist at LogicVision Inc. He received an MS degree in Computer Engineering from University of Southern California, a PhD in Electrical Engineering from McGill University, and an MBA from Wharton School of Business, University of Pennsylvania.
He is currently the President of IEEE Test Technology Technical Council (TTTC), the Past General Chair of the Design Automation Conference (DAC), the Editor-in-Chief Emeritus of Design & Test of Computers, the founder & chair of IEEE 1500 Standardization Working Group, and an Adjunct Professor at University of British Columbia. He served on the Board of Governors of Computer Society and CEDA, and as the Vice President of IEEE Computer Society. He has been founder and chair of a number of workshops and symposia, including the IEEE Workshops on 3D-IC Testing, Design-for-Manufacturability & Yield, Latin American Test Workshop, and East-West Design & Test Symposium.
Dr. Zorian holds 32 US patents, authored 4 books, published over 300 refereed papers and received numerous best paper awards. A Fellow of the IEEE since 1999, Dr. Zorian was the 2005 recipient of the prestigious Industrial Pioneer Award for his contribution to BIST, and the 2006 recipient of the IEEE Hans Karlsson Award for diplomacy. He is a member of the Academy of Sciences of Armenia. He received the IEEE Distinguished Services Award for leading the Test Technology Technical Council (TTTC).

Automatic Architecture Exploration of Massively Parallel MPSoCs
for Modern Cyber-Physical Systems

Prof. Lech Jóźwiak's photo Lech Jóźwiak
Associate Professor at the Eindhoven University of Technology
Eindhoven, The Netherlands

Abstract Recent progress in nano-dimension semiconductor technology enabled implementation of a very complex multi-processor system on a single chip (MPSoC). This facilitated a rapid progress in mobile and autonomous computing, global networking and wire-less communication. Numerous new sorts of cyber-physical systems became technologically feasible and economically justified. Various mobile and autonomous systems performing monitoring, control, communication, visualization or combination of these tasks and being parts of different objects, installations, machines or devices, or even being wearable or implanted in human or animal body can serve as examples. However, many of the new cyber-physical applications are very complex and heterogeneous, while at the same time they require a very high throughput or low reaction time, ultra-low energy consumption and high flexibility. The combination of the huge complexity with stringent requirements results in numerous serious design challenges, such as: accounting in design for more aspects and related complex multi-objective MPSoC optimization, adequate resolution of numerous complex design tradeoffs, reduction of the design productivity gap, time-to market and development costs without compromising the system quality, etc. To overcome these challenges both the system and design methodology have to be adequately adapted. The presentation introduces an advanced system technology being the industrial ASIP-based MPSoC technology of Intel Benelux, used a.o. in multiple newest generation smart-phones and tablets of many market leaders (e.g. Acer, Apple, Asus, Lava, Lenovo, NVIDIA, etc.), to subsequently discuss a new design methodology and design automation for this technology developed by the combined industry and academia consortium of the European research project ASAM (Automatic Architecture Synthesis and Application Mapping for MPSoCs based on adaptable ASIPs). After introducing a new ASAM design flow for the ASIP-based MPSoCs, the presentation focuses on the automatic architecture exploration of the ASIP-based sub-systems. In particular, it discusses several new tools developed by the research team of the presenter for the combined exploration of the application parallel structures and corresponding parallel ASIP architectures.

Author's bio Lech Jóźwiak received his M. Sc. and Ph. D. degrees from the Faculty of Electronics, Warsaw University of Technology, Poland, in 1976 and 1982, correspondingly. From 1976 he has been continuously working in the area of his specialization in academia, research institutes or industry in Poland, The Netherlands, USA, Canada and Australia. Currently he is an Associate Professor, Head of the Section of Digital Circuits and Formal Design Methods, in the Department of Electronic Systems, Eindhoven University of Technology, The Netherlands. He is an author of the methodology of quality-driven system design, information-driven approach to digital circuit synthesis, and theories of information relationships and measures, and general decomposition of discrete relations that have both a theoretical value and considerable practical importance. He is also a creator of several practical products in the fields of embedded systems and EDA tools. He is an author of more than 180 journal and conference papers, some book chapters, and presenter of numerous keynotes and tutorials at international conferences and summer schools. He is an Editor in Chief of the journal of “Microprocessors and Microsystems”, Director of EUROMICRO, Founder and Steering Committee Chair of the EUROMICRO Conference on Digital System Design, Advisory Committee and Organizing Committee member of the IEEE International Symposium on Quality Electronic Design; and program committee member of many other conferences. He is or was an advisor and consultant to the industry, Ministry of Economy, and Commission of the European Communities. He was a recipient of multiple Letters and Diplomas of Recognition for highly esteemed services and exceptional achievements from a.o. the Minister of Economy of Poland, presidents of professional societies and organizations (e.g. IEEE, EUROMICRO, ISQED, etc.) and chief editors of international scientific journals (e.g. IEEE Transactions on Computers; IEEE Transactions on CAD, etc.). In 2008 he was a recipient of the Honorary Fellow Award of the International Society of Quality Electronic Design for “Outstanding Achievements and Contributions to Quality of Electronic Design”.
Prof. Jóźwiak's full bio is available here.

Design and Testing of Integrated Circuit of Pixel Architecture
for Fast X-ray Imaging Applications

Prof. Paweł Gryboś's photo Paweł Gryboś
Professor at the AGH University of Science and Technology
Kraków, Poland

Abstract A hybrid pixel detector operating in a single photon counting mode requires a pixel readout chip with the geometry that matches the geometry of the detector array. Stringent and growing requirements on smaller pixel size, higher data throughput and more sophisticated functionality are imposed for such imaging systems. CMOS nanometer or 3D technologies seem to be very attractive for pixel readout integrated circuits, especially in the case of implementing more complex functionality or advanced algorithms on the chip. However, these technologies are mainly driven by high density and very fast digital circuits, nevertheless in case of hybrid pixel detectors the analog performance of front-end electronics, such as noise, offset spreads or crosstalk minimization, are of primary importance. We will present some examples of our realization of these kind of ICs both in advanced technologies (like 3D or 40 nm CMOS), as well as for commercial application where final yield is of primary importance.

Author's bio Paweł Gryboś received Ph.D. degrees in physics in 1995, D.Sc. degree in electronics in 2004 and professor title in 2011. His main research area are low-noise multichannel IC for biology, physics, and medical applications. As nanoscale technologies and 3D technologies are particularly attractive from the point of view of the density of multichannel ICs, prof. P. Gryboś has concentrated his research activity on them in recent years. He is the author of over 180 scientific publications including 56 papers from Journal Citation Report database, 3 monographs and 9 patents and patent applications. Some of his projects of the integrated circuits are also sold in commercial measurement systems by large companies with a global reach. Currently prof. P Gryboś leads his own Microelectronics Group (http://www.kmet.agh.edu.pl/www/asics) in the Department of Measurements and Electronics at the AGH University of Science and Technology in Kraków, Poland. In 2012, on the initiative of prof. P Gryboś the Chapter IEEE Solid-State Circuit Society in Poland was founded.